The use of photodiodes as photodetector elements in interline CCD image sensors is well known and has been discussed in various prior art documents. The problem of image lag and how a pinned-photodiode structure, in principle, can eliminate this lag has been discussed by N. Teranishi et al., in "No Image Lag Photodiodes Structure in the Interline CCD Image Sensor", in IEDM Tech. Dig., pages 324-327, December 1982. However, in practice there are various manufacturing and processing difficulties that lead to the creation of residual potential wells and barriers at the transfer gate edge that can actually preclude making these photodiodes lag free as discussed by B. C. Burkey et al., in "The Pinned Photodiode For An Interline-Transfer CCD Image Sensor", in IEDM Tech. Dig., pages 28-31, December, 1984. These difficulties arise from a general lack of self alignment of the photodiode implants to the transfer gate edge.
High-energy photodiode implants, using an n-type cathode layer, are used to simplify the process by eliminating long (in time), high-temperature drives as discussed by J. O. Borland and R. Koelsch, in "MeV Implantation Technology: Next Generation-Manufacturing With Current-Generation Equipment", Solid-State Technology, December 1993, and to improve sensitivity by creation of a larger collection volume. Although the associated larger ion range of these higher implant energies lead to better photodiodes, they present difficulties in terms of self alignment of the photodiode to the transfer gate edge, and in the elimination of residual potential wells and barriers required for lag-free operation.
It should be apparent from the foregoing discussion that there remains a need within the art for a product and a process for making self-aligned photodiodes using high-energy implants that results in improved performance and simplified manufacturing.